7/6/13 (Kyle)

7/6/13 (Kyle)

Things to do:

1.Run NPGS on sample with EL6 and see if I can still see the pattern, then we can eliminate the SiO2 layer possibility. If I don't see the pattern on EL6 then we know there is most likely a problem with the SiO2 layer.

2. Use furnace to grow new layers of SiO2 layers and compare to the last grown SiO2 layers. 

3. If I do see the pattern on the EL6 sample then I will try the EL6 again with perhaps a new pattern (thicker lines, longer lines, or vertical and horizontal lines together) If I don't see the pattern on EL6 then I assume the SiO2 layer is the problem and will try to pattern on a new PMMA sample.


Things that were done:

1. I used the same technique that we always have used to spin on the EL6 layer. 
    - It didn't look like the EL6 coating stuck on the wafer (very splotchy) so I tried spinning another layer on and got the same result. This leads me to believe that the problems with the patterning are due to the SiO2 layer.

2. 2 NPGS runs on EL6 sample. Pattern on the top of chip I used spot size 3 @ 1.5Kv and on the bottom of the chip I used spot size 1 @ 1.5Kv. When I went back to look for the pattern I had no luck in finding it. Because we were able to see the same pattern with the same spot size and settings I feel confident that the resist layer didn't stick to the wafer, most likely do to the thin or non existent layer of SiO2. This could mean that the resist layer must have a sufficient hydrophilic layer (SiO2) to adhere to. 

3. I used the 900C for 30min, 1200C for 1hr, 900C for 30min, to grow the SiO2 layer. When finished I didn't see the nice purple color I saw before, just a darker grey color. I decided to leave the wafers in the furnace at 1200C for 1.5hrs longer to see if the purple would show up with more time in the furnace. The purple layer was visible after the extra time in the furnace, so I believe the wafers have a nice thick layer of SiO2.