7/2/2013
Things to do:
1. Check results of yesterdays NPGS run on SEM
2. Set up new NPGS pattern with thicker lines and run NPGS on EL6 coated wafer.
3. Spin on CNTs
4. Check results of the EL6 NPGS run
5. Use furnace to grow SIO2 layer on 2 new wafers
Things that were done:
1. We could not locate the pattern on the PMMA coated wafer
- we believe our move step did not position the beam over our sample
2. Successfully used original pattern w/ spot size 3 @ 1.5 kV (blanker at position 3) to create a 4x4 array on the EL6 sample
3. Spun CNTs onto EL6 sample
- observed a few aligned CNTs on EL6 sample and took pictures (will try and post)
4. Again used original pattern but w/ spot size 1 @ 1.5 kV (blanker at position 3) to create a 4x4 array on the same EL6 sample.
5. Spun on CNTs
6. Cut and cleaned new wafers to be put into the furnace tomorrow morning (7/3/13)
*Note: add scale bar to all photos
01.2_AllignCNT_EL6_07_02
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