7/16/2013
Goal today:
1. Soak 3-4 chips (already covered in a resist layer and patterned using NPGS with the same pattern) + a chip with only a SiO2 layer in different solutions of CNTs. This will hopefully let us know if we actually need to spin on the CNTs or if dipping them in a solution of CNTs is a more effective way to stick CNTs and align with the pattern. This will also let us know which solution is best for aligning the CNTs.
2. Look at the sample from Friday and see if the pattern was actually exposed.
3.
What was accomplished:
1. Cleaned and spun on resist layer on 4 chips. Soaked one chip in SWCNT solution rinsed with DI water. Viewed and got a decent amount of CNTs to stick to our pattern. Next we will try soaking a chip in MWCNT.
Tuesday, July 16, 2013
Monday, July 15, 2013
7/15/2013
7/15/2013
Things to do:
1. Create the same pattern we used on Friday, five vertical lines with increasing doses (50, 100, 200, 400, 800 nC/cm. Make sure the array is a exact known distance from one corner of the the chip. Try and mark the chip by scratching one corner away from where the pattern is located. * In future scratch the chip just after baking on the resist layer but before dipping it in acetone: this will prevent silicon chips from contaminating the substrate surface.
2. Try dipping the substrate in a solution of CNTs instead of spinning them on with spin coater. We hope to see if the CNTs still stick to the pattern and if they align themselves with the orientation if the vertical lines.
Things that were completed:
1. Cleaned and spun EL6 on our Si/SiO2 substrate. Used electron beam lithography to pattern (5 vertical lines with increasing doses) an array in the center of our chip and another pattern 2000 microns in the positive y direction (up) and 6222.5 microns to the right (direct center on x axis) of the bottom left corner of our sample.
Things to do:
1. Create the same pattern we used on Friday, five vertical lines with increasing doses (50, 100, 200, 400, 800 nC/cm. Make sure the array is a exact known distance from one corner of the the chip. Try and mark the chip by scratching one corner away from where the pattern is located. * In future scratch the chip just after baking on the resist layer but before dipping it in acetone: this will prevent silicon chips from contaminating the substrate surface.
2. Try dipping the substrate in a solution of CNTs instead of spinning them on with spin coater. We hope to see if the CNTs still stick to the pattern and if they align themselves with the orientation if the vertical lines.
Things that were completed:
1. Cleaned and spun EL6 on our Si/SiO2 substrate. Used electron beam lithography to pattern (5 vertical lines with increasing doses) an array in the center of our chip and another pattern 2000 microns in the positive y direction (up) and 6222.5 microns to the right (direct center on x axis) of the bottom left corner of our sample.
Wednesday, July 10, 2013
7/10/13
7/10/13
Things to do:
1. Try a new pattern with vertical lines only. 4 lines (3,5,10, and 30 microns in length). Try 3 or more different arrays at time, all on the same chip to limit variables. We want to test different line doses and center to center spacing to see if either variable makes a difference to how many CNTs we are able to stick.
Things that were done:
1. Two NPGS runs both with spot size 1 at 1.5 kV. On the first run we had three arrays, the first array we used as a control with a line dose of 50 nC/cm (same line dose we have always used) and a center to center distance of 11.92nm (~12nm is what we have been using). The second array we changed the line dose to 75nC/cm. The third array we changed the center to center distance to 5.04nm. In the second run we used our first array as a control with the same settings as specified above. The second array we changed the line dose to 25nC/cm and the third array we changed the center to center distance to 3.21nm.
- All arrays resulted in very thick lines. My guess is that we were out of focus.
To fix for focus issues we should try and focus on a single silver nano particle and/or focus on multiple areas of the wafer.
2. Going to try one more run today to see if I can get the SEM in focus for NPGS and try the different arrays listed above.
Things to do:
1. Try a new pattern with vertical lines only. 4 lines (3,5,10, and 30 microns in length). Try 3 or more different arrays at time, all on the same chip to limit variables. We want to test different line doses and center to center spacing to see if either variable makes a difference to how many CNTs we are able to stick.
Things that were done:
1. Two NPGS runs both with spot size 1 at 1.5 kV. On the first run we had three arrays, the first array we used as a control with a line dose of 50 nC/cm (same line dose we have always used) and a center to center distance of 11.92nm (~12nm is what we have been using). The second array we changed the line dose to 75nC/cm. The third array we changed the center to center distance to 5.04nm. In the second run we used our first array as a control with the same settings as specified above. The second array we changed the line dose to 25nC/cm and the third array we changed the center to center distance to 3.21nm.
- All arrays resulted in very thick lines. My guess is that we were out of focus.
To fix for focus issues we should try and focus on a single silver nano particle and/or focus on multiple areas of the wafer.
2. Going to try one more run today to see if I can get the SEM in focus for NPGS and try the different arrays listed above.
7/08/13 & 7/09/13
7/08/13 & 7/09/13
Things to do:
1. We still need to find out if the SiO2 layer is the problem. Using the wafers with the newly grown SiO2 layer we can try the same old pattern with spot size 1 @ 1.5kV. If the pattern shows up we know we need a layer of SiO2 at least 100-300 nm thick.
2. Try a new pattern with horizontal and vertical lines to see which work better at aligning CNTs
Things that were done:
1. We saw the pattern on the wafer with the thicker layer of SiO2. We now know that we need a thicker layer of SiO2 (100-300nm thick) in order for the resist layer to stick to the wafer.
2. We used a pattern with 2 horizontal lines 25 microns in length, 2 horizontal lines 50 microns in length, 5 vertical lines 5 microns in length, and 5 vertical lines 10 microns in length.
-We found that the vertical lines had some tubes aligned at an angle like the ones found on the horizontal lines. The vertical lines also had entire CNTs stuck on the lines. This means the tubes were oriented in the same direction as the vertical lines. This could be very useful for aligning all of the tubes in the same direction and at specific locations. We will try more patterns with vertical lines in the next few days.
3. PMMA had the tendency to stick more nano tubes on it surface, but not necessarily the pattern itself. We decided to use EL6 as our resist layer since we want the CNTs on the lines only and not the surrounding area.
Things to do:
1. We still need to find out if the SiO2 layer is the problem. Using the wafers with the newly grown SiO2 layer we can try the same old pattern with spot size 1 @ 1.5kV. If the pattern shows up we know we need a layer of SiO2 at least 100-300 nm thick.
2. Try a new pattern with horizontal and vertical lines to see which work better at aligning CNTs
Things that were done:
1. We saw the pattern on the wafer with the thicker layer of SiO2. We now know that we need a thicker layer of SiO2 (100-300nm thick) in order for the resist layer to stick to the wafer.
2. We used a pattern with 2 horizontal lines 25 microns in length, 2 horizontal lines 50 microns in length, 5 vertical lines 5 microns in length, and 5 vertical lines 10 microns in length.
-We found that the vertical lines had some tubes aligned at an angle like the ones found on the horizontal lines. The vertical lines also had entire CNTs stuck on the lines. This means the tubes were oriented in the same direction as the vertical lines. This could be very useful for aligning all of the tubes in the same direction and at specific locations. We will try more patterns with vertical lines in the next few days.
3. PMMA had the tendency to stick more nano tubes on it surface, but not necessarily the pattern itself. We decided to use EL6 as our resist layer since we want the CNTs on the lines only and not the surrounding area.
Saturday, July 6, 2013
7/6/13 (Kyle)
7/6/13 (Kyle)
Things to do:
1.Run NPGS on sample with EL6 and see if I can still see the pattern, then we can eliminate the SiO2 layer possibility. If I don't see the pattern on EL6 then we know there is most likely a problem with the SiO2 layer.
2. Use furnace to grow new layers of SiO2 layers and compare to the last grown SiO2 layers.
3. If I do see the pattern on the EL6 sample then I will try the EL6 again with perhaps a new pattern (thicker lines, longer lines, or vertical and horizontal lines together) If I don't see the pattern on EL6 then I assume the SiO2 layer is the problem and will try to pattern on a new PMMA sample.
Things that were done:
1. I used the same technique that we always have used to spin on the EL6 layer.
- It didn't look like the EL6 coating stuck on the wafer (very splotchy) so I tried spinning another layer on and got the same result. This leads me to believe that the problems with the patterning are due to the SiO2 layer.
2. 2 NPGS runs on EL6 sample. Pattern on the top of chip I used spot size 3 @ 1.5Kv and on the bottom of the chip I used spot size 1 @ 1.5Kv. When I went back to look for the pattern I had no luck in finding it. Because we were able to see the same pattern with the same spot size and settings I feel confident that the resist layer didn't stick to the wafer, most likely do to the thin or non existent layer of SiO2. This could mean that the resist layer must have a sufficient hydrophilic layer (SiO2) to adhere to.
3. I used the 900C for 30min, 1200C for 1hr, 900C for 30min, to grow the SiO2 layer. When finished I didn't see the nice purple color I saw before, just a darker grey color. I decided to leave the wafers in the furnace at 1200C for 1.5hrs longer to see if the purple would show up with more time in the furnace. The purple layer was visible after the extra time in the furnace, so I believe the wafers have a nice thick layer of SiO2.
Things to do:
1.Run NPGS on sample with EL6 and see if I can still see the pattern, then we can eliminate the SiO2 layer possibility. If I don't see the pattern on EL6 then we know there is most likely a problem with the SiO2 layer.
2. Use furnace to grow new layers of SiO2 layers and compare to the last grown SiO2 layers.
3. If I do see the pattern on the EL6 sample then I will try the EL6 again with perhaps a new pattern (thicker lines, longer lines, or vertical and horizontal lines together) If I don't see the pattern on EL6 then I assume the SiO2 layer is the problem and will try to pattern on a new PMMA sample.
Things that were done:
1. I used the same technique that we always have used to spin on the EL6 layer.
- It didn't look like the EL6 coating stuck on the wafer (very splotchy) so I tried spinning another layer on and got the same result. This leads me to believe that the problems with the patterning are due to the SiO2 layer.
2. 2 NPGS runs on EL6 sample. Pattern on the top of chip I used spot size 3 @ 1.5Kv and on the bottom of the chip I used spot size 1 @ 1.5Kv. When I went back to look for the pattern I had no luck in finding it. Because we were able to see the same pattern with the same spot size and settings I feel confident that the resist layer didn't stick to the wafer, most likely do to the thin or non existent layer of SiO2. This could mean that the resist layer must have a sufficient hydrophilic layer (SiO2) to adhere to.
3. I used the 900C for 30min, 1200C for 1hr, 900C for 30min, to grow the SiO2 layer. When finished I didn't see the nice purple color I saw before, just a darker grey color. I decided to leave the wafers in the furnace at 1200C for 1.5hrs longer to see if the purple would show up with more time in the furnace. The purple layer was visible after the extra time in the furnace, so I believe the wafers have a nice thick layer of SiO2.
7/5/13 (Tran)
Update from Tran (I was out of lab on Friday)
1. Imaged our last sample with PMMA (from Wednesday). Unfortunately, I didn't see any line or any pattern at all. So I think there are few possibilities:
- I might have missed the pattern ( I almost exposed the whole chip to find the pattern but it's still one possibility)
- One more thing I notice, if we want to use different spot size, we probably want to change the spot size on the NPGS menu also, just right above where we enter the picoammeter current, we didn't do that last time when we change from spot size 3 to spot size 1. I think it makes a difference, the time was so much faster but I'm not sure if we're supposed to change it or not.
Wednesday, July 3, 2013
7/3/2013
7/3/2013
Things to do:
1. Check results of 2nd NPGS run on EL6 (Spot size 1, @1.5Kv)
2. Grow SiO2 layer on new samples using furnace.
- 900C for 30min, 1200C for 1hr, back to 900C for 30 min
3. Use wafer with freshly grown SIO2 and spin on PMMA layer
4. Run NPGS, same pattern on PMMA sample, spin on CNTs, and compare to the EL6 sample
Things that were done:
1. When looking at the EL6 sample (NPGS w/ spot size 1 @ 1.5 kV, blanker at position 3) we found that the pattern stopped after writing only 3 and a half lines. However we were able to see that a few CNTs were stuck on the lines. It didn't seem like as many CNTs stuck as when we used the spot size 3 this time but this could be because we only had three complete lines to compare.
- we believe this could be due to a lack of focus or even a pre exposure to the beam when viewing the original pattern on this particular sample.
2. When growing the SiO2 layer on the new substrate samples I noticed the SiO2 layer was not as visible as the last batch I completed. I used the same temperatures and times so I'm not sure why this is. Instead of a nice purple color (like my last batch), these were just a bit darker than the original Si wafers. Could dirty tubes play a role?? I may try leaving the next batch in the furnace a bit longer to see if that changes my results.
3. We had a bit of trouble focusing the beam and getting the faraday cup to read a reasonable number of pico amps, but with a bit of help from Oscar we were able to continue and pattern a 3x3 array on the PMMA sample. We spun on CNTs and have to wait until 7/4/13 or 7/5/13 to see how well the CNTs stuck.
- If either the PMMA or EL6 seems to have more aligned CNTs we will be able to rule out one of the variables and only use the more efficient resist from now on. This will give us the ability to start focusing on bake times and pattern sizes and orientation.
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